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ICS570
Multiplier and Zero Delay Buffer
Description
The ICS570 is a high-performance Zero Delay Buffer (ZDB) which integrates ICS' proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. The chip is part of ICS' ClockBlocksTM family, and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The device incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high impedance state. The ICS570 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices. The ICS570 A and B versions were designed to improve input to output jitter from the original ICS570M version, and are recommended for all new designs.
Features
* 8-pin SOIC package * Available in Pb (lead) free package (A and B versions
only)
* Pin-for-pin replacement and upgrade to ICS570M * Functional equivalent to AV9170 (not a pin-for-pin * * * * * * * * * * * *
replacement) Low input to output skew of 300 ps max (>60 MHz outputs) Ability to choose between 14 different multipliers from 0.5x to 32x Output clock frequency up to 168 MHz at 3.3 V Can recover degraded input clock duty cycle Output clock duty cycle of 45/55 Power Down and Tri-State Mode Passes spread spectrum clock modulation Full CMOS clock swings with 25 mA drive capability at TTL levels Advanced, low power CMOS process ICS570B has an operating voltage of 3.3 V (5%) ICS570A has an operating voltage of 5.0 V (5%) Industrial temperature version available
Block Diagram
IC L K S 1 :0
F B IN
d ivid e by N
Phase D e te c to r, C h a rg e Pum p, and Loop F ilte r
VCO /2
C LK
C LK2
E xte rn a l fe e d b a ck ca n co m e fro m C L K o r C L K /2 (se e ta b le o n p a g e 2 )
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Pin Assignment
S1 VDD GND ICLK 1 2 3 4 8 7 6 5 CLK/2 CLK S0 FBIN
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
FBIN from CLK S1 S0 #1 0 0 0 M M M 1 1 #6 0 M 1 0 M 1 0 M x3 x4 x8 x6 x10 x1 x16 CLK pin #7 CLK2 pin #8 x1.5 x2 x4 x3 x5 /2 x8 FBIN from CLK/2 CLK pin #7 x6 x8 x16 x12 x20 x2 x32 CLK2 pin #8 x3 x4 x8 x6 x10 x1 x16 3.75 to 28 2.75 to 19 2.5 to 9.5 2.5 to 12.5 2.5 to 7.5 11 to 75 2.5 to 5 5.5 to 37.5 2.5 to 25 2.5 to 19 2.5 to 9.5 2.5 to 12.5 2.5 to 7.5 5 to 75 2.5 to 5 2.5 to 37.5 ICS570B (3.3 V) ICS570A (5.0 V)
ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
Power Down and Tri-State
1 1 x2 x1 x4 x2 0 = connect directly to ground M = leave unconnected (self-biases to VDD/2) 1 = connect directly to VDD *Input range with CLK feedback is double that for CLK/2
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8
Pin Name
S1 VDD GND ICLK FBIN S0 CLK CLK/2
Pin Type
Input Power Power Input Input Input Output Output
Pin Description
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above. Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A). Connect to ground. Reference clock input. Feedback clock input. Select 0 for output clock. Connect to GND, VDD, or float per decoding table above. Clock output per table above. Clock output per table above. Low skew divide by two of pin 7 clock.
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
External Components
The ICS570 requires a 0.01F decoupling capacitor to be connected between VDD and GND. It must be connected close to the part to minimize lead inductance. No external power supply filtering is required for this device. A 33 series terminating resistor can be used next to each output pin.
Recommended Circuit
S1 VDD GND S0 Input FBIN
CLK/2 x2 Mode (S1, S0 = 1, 0) CLK/2 Feedback CLK
CLK CLK/2
ICLK
ICLK
CLK
CLK/2 x2 Mode (S1, S0 = 1, 1) CLK Feedback
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the CLK/2 could be a falling edge compared with ICLK. ICS recommends using CLK/2 feedback whenever possible. This will synchronize the rising edges of all three clocks.
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Clock Period Jitter Tables (ICS570A)
All jitter values are considered typical measured at 25C with 27 termination resistor and 15 pF loads on both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
CLK = 50M S1 S0 0 0 M M M 1 1 1 M 1 0 M 1 0 M 1 CLKIN (MHz) 8.333 6.25 3.125 4.167 2.5 25 1.5625 12.5 Multiplier 6x 8x 16x 12x 20x 2x 32x 4x P to P 115 115 120 120 120 120 120 120 1 sigma 80 80 80 90 80 70 80 80 Multiplier 3x 4x 8x 6x 10x 1x 16x 2x CLK/2 = 25M P to P 65 60 55 60 60 55 50 55 1 sigma 20 20 20 20 20 20 20 20
Absolute and One Sigma Jitter (ps)
CLK = 100M S1 S0 0 0 M M M 1 1 1 M 1 0 M 1 0 M 1 CLKIN (MHz) 16.667 12.5 6.25 8.333 5 50 3.125 25 Multiplier 6x 8x 16x 12x 20x 2x 32x 4x P to P 135 140 140 140 135 120 135 130 1 sigma 100 100 110 110 100 90 100 90 Multiplier 3x 4x 8x 6x 10x 1x 16x 2x CLK/2 = 50M P to P 55 50 55 55 50 50 55 65 1 sigma 20 20 20 20 20 20 20 20
Absolute and One Sigma Jitter (ps)
CLK = 150M S1 S0 0 0 M M M 1 1 1 M 1 0 M 1 0 M 1 CLKIN (MHz) 25 18.375 9.375 12.5 7.5 75 4.6875 37.5 Multiplier 6x 8x 16x 12x 20x 2x 32x 4x P to P 160 165 170 160 160 155 165 160 1 sigma 120 120 120 120 120 110 120 110 Multiplier 3x 4x 8x 6x 10x 1x 16x 2x CLK/2 = 75M P to P 55 55 50 55 55 55 55 50 1 sigma 20 20 20 20 20 20 20 20
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Clock Period Jitter Tables (ICS570B)
All jitter values are considered typical measured at 25C with 27 termination resistor and 15 pF loads on both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
CLK = 50M S1 S0 0 0 M M M 1 1 1 M 1 0 M 1 0 M 1 CLKIN (MHz) 8.333 6.25 3.125 4.167 2.5 25 1.5625 12.5 Multiplier 6x 8x 16x 12x 20x 2x 32x 4x P to P 110 125 130 120 115 130 120 120 1 sigma 80 90 90 90 90 50 90 60 Multiplier 3x 4x 8x 6x 10x 1x 16x 2x CLK/2 = 25M P to P 55 50 55 55 55 55 55 55 1 sigma 20 20 20 20 20 20 20 20
Absolute and One Sigma Jitter (ps)
CLK = 100M S1 S0 0 0 M M M 1 1 1 M 1 0 M 1 0 M 1 CLKIN (MHz) 16.667 12.5 6.25 8.333 5 50 3.125 25 Multiplier 6x 8x 16x 12x 20x 2x 32x 4x P to P 100 100 110 100 105 90 95 105 1 sigma 70 70 80 70 70 60 70 70 Multiplier 3x 4x 8x 6x 10x 1x 16x 2x CLK/2 = 50M P to P 45 45 45 45 40 40 45 60 1 sigma 20 20 20 20 20 20 20 20
Absolute and One Sigma Jitter (ps)
CLK = 150M S1 S0 0 0 M M M 1 1 1 M 1 0 M 1 0 M 1 CLKIN (MHz) 25 18.375 9.375 12.5 7.5 75 4.6875 37.5 Multiplier 6x 8x 16x 12x 20x 2x 32x 4x P to P 115 120 130 130 130 115 130 110 1 sigma 70 80 90 90 90 90 90 70 Multiplier 3x 4x 8x 6x 10x 1x 16x 2x CLK/2 = 75M P to P 50 50 50 45 45 45 50 60 1 sigma 20 20 20 20 20 20 20 20
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS570. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature, Commercial version Ambient Operating Temperature, Industrial version Storage Temperature Junction Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature, Commercial version Ambient Operating Temperature, Industrial version Power Supply Voltage (measured in respect to GND)
Min.
0 -40 +3.15
Typ.
Max.
70 +85
Units
C C V
+3.3
+3.45
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Operating Voltage Operating Current
Symbol Conditions
VDD IDD ICS570B ICS570A ICS570B 3.3 V, 50M input, S1:0 = 11 ICS570A 5.0 V, 50M input, S1:0 = 11
Min.
3.15 4.75
Typ.
Max.
3.45 5.25
Units
V mA
16
25
mA
Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage (mid-level)
VIH VIL VIH VIM
ICLK, FBIN ICLK, FBIN S0, S1 S0, S1
2 0.8 VDD-0.5 VDD/2
V V V V
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Parameter
Input Low Voltage Output High Voltage (CMOS High) Output High Voltage Output Low Voltage Short Circuit Current Input Capacitance
Symbol Conditions
VIL VOH VOH VOL IOS CIN S0, S1 IOH = -4 mA IOH = -12 mA IOL = 12mA Each output S0, S1
Min.
VDD-0.4 2.4
Typ.
Max.
0.5
Units
V V V
0.4 100 5
V mA pF
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Input Frequency, ICLK Output Clock Frequency Output to Output Skew Output to Output Skew Input to Output Jitter
Symbol
Conditions
FBIN from CLK/2 CLK ICS570B ICS570A 40 - 150 MHz ICLK to FBIN, CLK>30MHz, Note 1
Min.
10
Typ.
Max. Units
168 MHz ps ps ps 300 600 1 1.5 ps ps ns ns ns ns 55 %
See table on page 2 100 100 100-250 -300 -600 -1 -1.5 0.75 0.75 45 49 - 51 175 200
Input Skew, ICS570B
ICLK to FBIN, CLK<10MHz, Note 1 ICLK to FBIN CLK>30MHz, Note 1
Input Skew, ICS570A Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle
ICLK to FBIN, CLK<10MHz, Note 1 0.8 to 2.0V, Note 2 2.0 to 0.8V, Note 2 at VDD/2
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2 Note 2: Measured with 27 terminating resistor and 15 pF loads
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
150 140 120 40
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters Symbol A A1 B C D E e H h L Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
h x 45
Inches Min Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
E INDEX AREA
H
12 D
A A1
C
-Ce
B SEATING PLANE L
.10 (.004)
C
MDS 570 I
8
Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
ICS570 Multiplier and Zero Delay Buffer
Ordering Information
Part / Order Number
ICS570A ICS570AT ICS570AI ICS570AIT ICS570AILF ICS570AILFT ICS570ALF ICS570ALFT ICS570B ICS570BT ICS570BLF ICS570BLFT ICS570BI ICS570BIT ICS570BILF ICS570BILFT ICS570M ICS570MT ICS570MI ICS570MIT
Marking
ICS570A ICS570A ICS570AI ICS570AI 570AILF 570AILF 570ALF 570ALF ICS570B ICS570B ICS570BL ICS570BL ICS570BI ICS570BI 570BILF 570BILF ICS570M ICS570M ICS570MI ICS570MI
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to 85 C -40 to 85 C -40 to 85 C -40 to 85 C 0 to +70 C 0 to +70 C -40 to 85 C -40 to 85 C
"LF" denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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